The truth table of a sequential circuit is the map that links the current state and the input to the next state and the output. Still, when you are asked to complete such a table, you usually already have some of the rows written out—often the transitions that are obvious from the logic diagram or from a state‑chart. In real terms, the missing rows are those that arise from the combinational logic that drives the next‑state logic, the output logic, or from the way the flip‑flops are clocked. This article walks you through a systematic approach to fill in all the missing entries, using a concrete example that illustrates every step Simple as that..
1. Understand the Circuit Layout
Before you even touch a sheet of paper, spend a few minutes looking at the schematic:
- Identify the storage elements – usually D, T, JK, or SR flip‑flops.
- Count the bits of state – the number of flip‑flops tells you how many bits the state vector has.
- Locate the input signals – name them clearly (e.g., A, B, C).
- Follow the combinational logic that drives the flip‑flop inputs and the output pins.
- Check the clock – is it a single clock for all flip‑flops, or are there multiple clock domains? For a typical exercise, a single clock is assumed.
By the end of this step you should have a mental model: State → Next‑state logic → Output logic The details matter here. That alone is useful..
2. Define the State Variables
Let’s assume the circuit has two D flip‑flops, so the state is represented by two bits, Q₁ (MSB) and Q₀ (LSB). The state space thus contains four possible combinations:
| State | Q₁ | Q₀ |
|---|---|---|
| 0 | 0 | 0 |
| 1 | 0 | 1 |
| 2 | 1 | 0 |
| 3 | 1 | 1 |
Give each state a convenient name (e.g., S₀, S₁, S₂, S₃) if that helps you keep track.
3. Extract the Next‑State Logic Equations
Read the logic that feeds the D inputs of the flip‑flops. Suppose the schematic shows:
- D₁ (input to Q₁) = A · Q₀ + B̅ · Q₁
- D₀ (input to Q₀) = A ⊕ Q₁
Where:
- “·” denotes AND
- “+” denotes OR
- “⊕” denotes XOR
- B̅ is the complement of B
These equations tell you what next‑state bits (D₁, D₀) will be after the clock edge, given the current state and the inputs.
4. Write the Partial Truth Table
Create a table with columns for:
- Current State (Q₁, Q₀)
- Inputs (A, B)
- Next‑State (D₁, D₀)
- Output (if any)
If the exercise already gives you some rows, copy them verbatim. For the missing rows, fill in the blanks with variables or placeholders It's one of those things that adds up..
| Q₁ | Q₀ | A | B | D₁ | D₀ | Output |
|---|---|---|---|---|---|---|
| 0 | 0 | |||||
| 0 | 1 | |||||
| 1 | 0 | |||||
| 1 | 1 |
5. Enumerate All Combinations of Inputs
If the circuit has two input bits (A and B), there are 2² = 4 input combinations. For each state, you must evaluate the next‑state logic for each input vector. A systematic way is to create a nested loop: outer loop over states, inner loop over input vectors Practical, not theoretical..
| Q₁ | Q₀ | A | B | D₁ | D₀ |
|---|---|---|---|---|---|
| 0 | 0 | 0 | 0 | ||
| 0 | 0 | 0 | 1 | ||
| 0 | 0 | 1 | 0 | ||
| 0 | 0 | 1 | 1 | ||
| 0 | 1 | 0 | 0 | ||
| … | … | … | … | … | … |
Fill this expanded table first; it is easier to spot patterns and verify consistency Worth keeping that in mind..
6. Compute Next‑State Bits
Apply the equations from step 3 to each row. Use Boolean algebra or a truth‑table calculator. To give you an idea, for state S₀ (Q₁=0, Q₀=0) and inputs A=1, B=0:
- D₁ = A · Q₀ + B̅ · Q₁ = 1 · 0 + 1 · 0 = 0
- D₀ = A ⊕ Q₁ = 1 ⊕ 0 = 1
So the next state will be (Q₁=0, Q₀=1) Easy to understand, harder to ignore..
Repeat this calculation for every row. Carefully check that you’ve applied the complement (B̅) correctly; a common pitfall is to forget the bar Not complicated — just consistent..
7. Derive the Output Logic
If the circuit has an output, read the logic that drives it. Suppose the output Z is defined as:
- Z = Q₁ · A + Q₀ · B̅
Now, for each row, substitute the current state bits and the input values to compute Z. Add the result to the table.
8. Verify Consistency
Once the table is filled, check for logical consistency:
- No contradictions – the same state/input pair should never produce two different next states or outputs.
- Determinism – for a synchronous sequential circuit, each row must lead to a unique next state.
- Completeness – every possible combination of state and inputs should be represented.
If you spot a contradiction, revisit the logic equations; a mis‑typed gate or a missing inversion is often the culprit.
9. Consolidate Into the Final Truth Table
After verification, collapse the expanded table back into the compact form, grouping rows that share the same next state and output. The final table should look like this:
| Current State | Inputs | Next State | Output |
|---|---|---|---|
| 00 | 00 | 00 | 0 |
| 00 | 01 | 01 | 0 |
| 00 | 10 | 01 | 1 |
| 00 | 11 | 01 | 1 |
| 01 | 00 | 10 | 0 |
| … | … | … | … |
This is the bit that actually matters in practice Worth keeping that in mind..
Feel free to add a row‑header that lists the state name (S₀, S₁, etc.) for readability.
10. Illustrate With a State‑Transition Diagram
A truth table is great for calculations, but a diagram makes the behavior intuitive. Draw a directed graph where:
- Nodes represent states (S₀, S₁, S₂, S₃).
- Arrows represent transitions, labeled with the input that triggers them.
- Mark the output on each arrow or node, depending on whether the output is combinational or state‑dependent.
This visual aid is especially helpful when explaining the circuit to someone new to sequential logic Simple, but easy to overlook..
11. Common Pitfalls to Avoid
| Pitfall | How to Spot | Fix |
|---|---|---|
| Missing input combinations | Some states will have fewer than 4 rows. | |
| Incorrect complement | B̅ appears as B in some rows. In real terms, | Re‑evaluate the Boolean expression. |
| Output mis‑placement | Output depends on next state instead of current state. | Double‑check the input enumeration. Because of that, |
| Clock‑edge misunderstanding | Next state uses current state values but should use previous state. | Verify the output logic source in the schematic. |
12. FAQ
Q1: What if the circuit has more than two flip‑flops?
The same method applies. Increase the number of state bits, expand the table accordingly, and use the corresponding next‑state equations.
Q2: Can I use Karnaugh maps to simplify the next‑state logic?
Absolutely. Once you have the truth table, you can derive simplified Boolean expressions for D₁, D₀, and the output using Karnaugh maps or logic minimization tools.
Q3: How do I handle asynchronous inputs?
If an input can change the state without a clock edge, it is asynchronous. In the truth table, treat the asynchronous input as a separate column and note that the state changes immediately when it toggles.
13. Takeaway
Completing a truth table for a sequential circuit is a disciplined exercise in reading logic, enumerating possibilities, and applying Boolean algebra. By following these structured steps—understanding the schematic, defining state variables, extracting equations, enumerating inputs, computing next states, deriving outputs, verifying consistency, and visualizing the result—you’ll produce a reliable, error‑free table that serves as the backbone for analysis, simulation, and documentation Turns out it matters..
Your final truth table is not just a list of numbers; it is a concise map of how the circuit behaves under every conceivable circumstance, enabling designers and developers to predict, debug, and optimize the system with confidence.
